In wide Static Random Access Memory (SRAM) devices, the number of columns of memory cells can be very high. When a word line traverses across the high number of memory cells, the word line is subjected to a large amount of impedance (e.g., from the gate capacitances of the SRAM latch access transistors). In small process technologies (e.g., 16 nanometer), it is difficult to ensure that the ends of the word lines that are farthest away from the word line drivers achieve an acceptable slope. In some cases, the far ends of the word lines are unable to reach the supply rail voltage of the drivers, which reduces the noise margin for memory cells located at the far ends. While word lines can often include re-buffers to boost the word line signals (e.g., a series pair of inverters in a word line signaling path), the re-buffers introduce propagation delays, which decreases the performance of the SRAM devices.